This invention relates to schemes for interconnecting integrated circuit chip packages to circuit boards. More particularly, this invention relates to novel and improved schemes for interconnecting integrated circuit chip packages (such as land grid array type integrated circuit packages) having a center space under the chip package for housing a component which is sandwiched between the chip package and a circuit board.
It is well known in the field of micro-electronics that high frequency operation, particularly the switching of integrated circuits, can result in transient energy being coupled into the power supply circuit. Generally the prevention of the coupling of undesired high frequency noise or interference into the power supply for an integrated circuit is accomplished by connecting a decoupling capacitor between the power and the ground leads of the integrated circuit (IC).
One connection scheme which has been found to be quite successful is to mount a decoupling capacitor underneath an integrated circuit. Such decoupling capacitors are commonly available from Rogers Corporation, (assignee of the present application) and are sold under the trademark MICRO Q. Examples of these decoupling capacitors are found in U.S. Pat. Nos. 4,475,143; 4,502,101 and 4,748,537 all of which are assigned to the assignee hereof.
U.S. Pat. Nos. 4,626,958; 4,667,267; 4,658,327; 4,734,818; 4,734,819; 4,853,826 and 4,853,827 are also assigned to the assignee hereof and incorporated herein by reference. These patents disclose decoupling capacitors which are particularly well suited for pin grid array (PGA) and plastic leaded chip carrier packages. For example, the PGA decoupling capacitor of U.S. Pat. No 4,853,826 comprises a dielectric material sandwiched between a pair of conductors. A group of flat strips or skirts extend outwardly a short distance generally in the plane of the metal conductors to which they are attached and are then bent downwardly so as to extend in the direction which is perpendicular to the planes of the conductors. The entire assembly, with the exception of the flat strips (i.e., leads), may then be encapsulated within a suitable non-conductive material.
This flat decoupling capacitor adapted for mounting directly under the PGA package results in a lower decoupling loop, thus a more effective decoupling scheme. The capacitor of U.S. Pat. No. 4,853,826 also contributes to a savings in board space, i.e., takes up less "real estate" on the printed circuit board, by resting entirely underneath the PGA package.
It will be appreciated that the aforementioned decoupling capacitors are well suited for use in conjunction with PGA packages.
The land grid array (LGA) package is a ceramic leadless package (basically a pin-less version of a PGA package) which reduces propagation delays and other detrimental effects. The LGA package is generally smaller than its PGA counterpart (for the same number of I/O's) and has connection pads in a pitch matrix array (e.g., 0.050" pitch matrix array). The LGA package is installed (surface mounted) onto the printed circuit board (PCB), on a corresponding array of conductor pads which in turn are connected to the rest of the board circuitry by traces or otherwise.
The actual mechanical and electrical attachment of the LGA package to the PCB is accomplished by means of solder or by some connector system. One of the disadvantages of solder attachment is that the solder joints cannot be inspected and that flux residue cleaning is extremely difficult, due to the very small gap between the LGA package bottom surface and the surface of the PCB.
Also, in many applications, it is necessary or desirable to replace the IC package (LGA) to reconfigure the digital system (e.g., computers, industrial control, etc) or to upgrade it, thus requiring a connector system. Such a pad-to-pad demateable connector system is commonly available from Rogers Corporation, (assignee of the present application) and is sold under the trademark ISOCON. This system comprises a piece of silicone elastomeric material with an array of rectangular apertures or holes drilled at an angle with respect to the top and bottom surfaces. A generally "S" shaped conductor pin is inserted into each aperture. The connector operates under the principle of compressing the elastomer piece, making the "S" shaped conductor pins rotate slightly, thus providing the required "wipe" action to the LGA and PCB contacts. The elastomeric material provides the necessary spring back force to achieve an effective mechanical contact as well as a low resistance contact between the LGA and PCB pads. A hardware system is provided to control and maintain the compression of the elastomeric material and to provide alignment and registration between the LGA contacts and the PCB pads. This type of connector system is disclosed in U.S. Pat. No. 4,793,814, also assigned to assignee hereof and incorporated herein by reference.
Present decoupling practice for LGA package systems is to use one or several ceramic multi-layer chip (MLC) capacitors surface mounted on the PCB surrounding the LGA/Connector System. This practice suffers from several disadvantages. For example, the MLC capacitors, due to the area of the PCB occupied by the connector system itself, end up being located at relatively large distances from one another, i.e., the length of the electrical connections (made typically through the voltage and ground planes of the PCB) between the MLC capacitors and the voltage and ground pads of the PCB (connecting to the LGA) is large. This introduces large inductance in the decoupling loop, which results in noise in the power ground circuitry of the IC.
While well suited decoupling schemes for PGA packages are disclosed, a need exists for an improved decoupling scheme for use in conjunction with land grid array (LGA) type integrated circuit packages as well as for other IC chip packages having a central void or space therein.